Design of low power network on chip using data encoding techniques
An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC makers at all of this into one chip. A contrast of Network On Chip’s (NoC’s) structure makes a fitting replacement for System On Chip (SoC) design in designs incorporating large number of processing cores. In NoC the overall power dissipation is due to the interconnection system. The interconnects have become main element in dynamic power dissipation in a NoC design. NoC improves the scalability of SoC and the power efficient of complex SoC compared to other designs.